home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
The World of Computer Software
/
The World of Computer Software.iso
/
8250.zip
/
8250.DOC
next >
Wrap
Text File
|
1988-06-27
|
19KB
|
368 lines
Note: References to Stargate are specific to that multi serial port board.
References to the 8250 apply to all 8250 UART chips. Some comments may
indicate that a specific condition is needed a a specific serial board.
Below are some UNTESTED routines which I believe will help in setting
some com parameters. These routines have not reached the debug stage,
so no gaurantees. I was originally writting this for a complex system
which would address several serial port locations, port[port_num] in the
routines below refer to the base port address of the specific 8250 chip.
That project has been put on hold at the present time. I present this
information to the BBS comunity because recent programs have produced
8250 transfer rates at speeds of 115K+ baud, much above documented
transfer rates which are deemed realistic. These programs appear to function
without any adverse conditions at these rates. So, I hope all hackers can
delight in the information which follows.
These routines were written in TURBOC Ver 1.5 and are given only to show
how I believe setting the parameters could be done. Again, These routines
have not been tested or debugged.
STARGATE OC8000 SETTINGS
PORT ADDRESSES HEX LOCATION 1 HEX LOCATION 2
PORT 1 180 3F8 (Normally COM1)
PORT 2 188 2F8 (Normally COM2)
PORT 3 190 280
PORT 4 198 288
PORT 5 1A0 290
PORT 6 1A8 298
PORT 7 1B0 2A0
PORT 8 1B8 2A8
Interrupt
Status Register 580 7F8
HARDWARE INTERRUPT SET TO IRQ3 (used by COM2 devices) OR
HARDWARE INTERRUPT SET TO IRQ4 (used by COM1 devices) OR
HARDWARE INTERRUPT IRQ2 MAY BE USED IF IT IS NOT TAKEN BY ANOTHER
DEVICE, THUS PRESERVING COM1,COM2 PORTS AS NORMAL.
HIGHER IRQ SETTINGS NOT RECOMMENDED SINCE THEY HAVE LOWER PRIORITIES
AND/OR MAY BE TAKEN BY OTHER DEVICES. A LIST OF HARDWARE IRQ
ASSIGNMENTS IN DOS ARE SHOWN BELOW.
Switch Settings on OC8000 board:
( Set one of the switches 1-6 to on to set IRQ# )
( Lowest IRQ has highest interrupt priority. )
Dip Switch 1 Location 1 Location 2 IRQ
8 OFF ON
7 ON ON SEE DOC
(--------- CHOOSE ONE ONLY --------)
6 ON SETS OFF DISABLES IRQ 7
5 ON SETS OFF DISABLES IRQ 6
4 ON SETS OFF DISABLES IRQ 5
3 ON SETS OFF DISABLES IRQ 4
2 ON SETS OFF DISABLES IRQ 3
1 ON SETS OFF DISABLES IRQ 2
Dip Switch 2 sets number of uarts in last 4 positions.
OC 8000 board with # UARTS; DS2 SWITCH POS.
UART LOCATION NUM 1 2 3 4
4 ON ON ON ON
TOP 5 OFF ON ON ON
SECOND FROM TOP 6 OFF OFF ON ON
SECOND FROM BOTTOM 7 OFF OFF OFF ON
BOTTOM 8 OFF OFF OFF OFF
In looking at the OC8000 board, these switches appear to fix pin
30 of the 8250 chip to ground. This is the interrupt pin that goes
high when any of the allowed IER interrupts occur on the 8250.
Grounding this pin effectively disables any hardware interrupts
being sent to the CPU via the Stargate Interrupt Status Register.
-------------------------------------------------------------------------------
== General IBM Hardware interrupt locations. PC-XT and AT ==
Hardware Interrupt Vector memory locations and number: DOS 2.X - 3.X
IRQ Number
(hex) - (Decimal)
IRQ0 System Timer Tick Attention - 0x20 - 8
IRQ1 Keyboard Attention - 0x24 - 9
IRQ2 Reserved for future use - 0x28 - 10
IRQ3 Com2 Attention - 0x2C - 11
IRQ4 Com1 Attention - 0x30 - 12
IRQ5 Harddisk Attention - 0x34 - 13
IRQ6 Disk controller Attention - 0x38 - 14
IRQ7 Parallel Printer Attention - 0x3C - 15
-------------------------------------------------------------------------------
===============================================================================
Detailed 8250A register locations for performing IO.
BASE+0 TX CHARACTER BUFFER if DLAB=0
--------------------------------------------------------------
BASE+0 LSB DIVSOR LATCH if DLAB=1
--------------------------------------------------------------
BASE+0 RX CHARACTER BUFFER if DLAB=0
--------------------------------------------------------------
BASE+1 MSB DIVSOR LATCH if DLAB=1
--------------------------------------------------------------
BASE+1 INTERRUPT ENABLE REG if DLAB=0 (IER)
ENABLES FOUR 8250 INTERRUPT TYPES TO SEPERATELY ACTIVATE
THE CHIP (INTRPT) OUTPUT SIGNAL. A 0 IN BITS 0-3 DEACTIVATE
ALL INTERRUPTS, AND PLACING A 1 IN ANY BIT 0-3 ACTIVATES
THE INTERRUPT.
D7=0
D6=0
D5=0
D4=0
D3= ENABLE MODEM STATUS INTERRUPT
D2= ENABLE RECEIVE LINE STATUS INTERRUPT
D1= ENABLE TX HOLDING REGISTER INTERRUPT
D0= ENABLE RECEIVE DATA AVAILABLE INTERRUPT
--------------------------------------------------------------
BASE+2 INTERRUPT ID REGISTER (IIR)
D7=0
D6=0
D5=0
D4=0
D3=0
D2-D1 INDICATES THE HIGHEST 8250A INTERNAL INTERRUPT
PENDING. SUMMARIZED BELOW.
D0= 0=INDICATES INTERRUPT PENDING.
1=INDICATES NO INTERRUPT PENDING.
BIT 2 1 0 PRIORITY INTERRUPT INTERRUPT RESET
TYPE SOURCE CONTROL
--------------------------------------------------------------
1 1 0 HIGHEST RX LINE STATUS OVERRUN, READ
PARITY, LINE
FRAMEING STATUS
ERRORS, REGISTER
OR BREAK
INTERRUPT
--------------------------------------------------------------
1 0 0 SECOND RECEIVED RECEIVER READ
DATA DATA RECEIVER
AVAILABLE READY BUFFER
REGISTER
--------------------------------------------------------------
0 1 0 THIRD TX HOLDING TX HOLDING READ
REGISTER IS REGISTER IS (IIR) IF
EMPTY EMPTY SOURCE OF
INTERRUPT
OR
WRITE TO
TX HOLDING
REGISTER
-----------------------------------------------------------------
0 0 0 FOURTH MODEM STATUS CTS,DSR, READ
RING MODEM
INDICATOR, STATUS
OR RECEIVE REGISTER
LINE SIGNAL
DETECT
--------------------------------------------------------------
BASE+3 LINE CONTROL REG (LCR)
DLAB state=bit 7
D7; DLAB
D6; 0=break disabled.
1=break enabled.
D5; 0=parity disabled.
1=parity enabled.
D4; 0=odd parity.
1=even parity.
D3; 0=no parity.
1=parity.
D2; 0=1 stop bit.
1=2 stop bits if bits/char > 5, else 1.5 stop bits.
D1-0;00=5 bits/char
01=6 bits/char
10=7 bits/char
11=8 bits/char
--------------------------------------------------------------
BASE+4 MODEM CONTROL REG (MCR)
IMPORTANT:
Bit 3 must be 0 to allow for IRQ in the Interrupt Enable Reg.
to take place.
D7=0;
D6=0;
D5=0;
D4; Loopback for internal testing of the 8250 chip.
In diagnostic mode when set to 1;
Diagnostics off when reset to 0 (Normal Operation);
D3; Controls User Designated OUT2 signal output.
(8250 UART PIN 34)
(Not used on Stargate Card OC8000)
(Must be 0 to allow IER interrupts on IBM cards,
don't know about others.)
When set to 1, OUT2 output forced to logic 0.
When reset to 0, OUT2 output forced to logic 1.
D2; Controls User Designated OUT1 signal output.
(8250 UART PIN 34)
(Not used on Stargate Card OC8000)
When set to 1, OUT1 output forced to logic 0.
When reset to 0, OUT1 output forced to logic 1.
D1; Controls RTS output.
(8250 UART PIN 32, RS232C PIN 4)
(Available on Stargate OC8000 Port 1 only)
When set to 1, RTS output forced to logic 0.
When reset to 0, RTS output forced to logic 1.
D0; Controls DTR output.
(8250 UART PIN 33, RS232C PIN 20)
(Available on Stargate OC8000 Port 1 only)
When set to 1, DTR output forced to logic 0.
When reset to 0, DTR output forced to logic 1.
--------------------------------------------------------------
BASE+5 LINE STATUS REG (LSR) LOGIC STATES;
D7=0
D6=TX SHIFT REG EMPTY(TSRE) 1=TSRE IDLE
0=DATA TRANSFER FROM
THRE TO TSRE.
D5=TX HOLDING REG EMPTY (THRE) READY TO EXCEPT NEW CHAR
1=ISSUES IRQ TO CPU, SET
WHEN CHAR IS TRANSFERRED
FROM THRE TO TSRE.
0=RESET WHEN THRE LOADED
FROM CPU.
(Bits 1-4 are error conditions that produce a Receiver
Line Status Interrupt when their conditions are detected)
D4=BREAK INTERRUPT (BI) 1=RECEIVED DATA HELD LONGER
THAN SPACING STATE(Logic 0)
FOR LONGER THAN FULL WORD
TRANSMIT TIME.
D3=FRAMING ERROR (FE) 1=INDICATES INVALID STOP
BIT, STOP BIT DETECTED AS
PIN 31 8250A 0 (SPACING LEVEL) FOLLOWING
LAST DATA OR PARITY BIT.
D2=PARITY ERROR (PE) 1=INDICATES WRONG PARITY AS
SELECTED IN LINE CONTROL
PIN 34 8250A REG. RESET BY HAVING CPU
READ LINE STATUS REGISTER.
D1=OVERRUN ERROR (OE) 1=DATA IN RECEIVE BUFFER REG
RTS PIN 4 RS232 NOT READ BY CPU BEFORE NEXT
PIN 32 8250A CHAR TRANSFERRED INTO THE
RECEIVE BUFFER REG, THUS
DESTROYING PREVIOUS CONTENTS.
RESET BY READING LINE STATUS
REGISTER.
D0=DATA READY (DR) 1=INDICATES A COMPLETE CHARACTER
DTR PIN 20 RS232 HAS BEEN RECEIVED AND PLACED
PIN 33 8250A INTO THE RECEIVE BUFFER REG.
RESET BY READING (RBR) OR
WRITING A 0 TO THIS BIT BY CPU.
--------------------------------------------------------------
PINS ON - RS232 8250A
BASE+6 MODEM SATUS REG (MSR)
D7= (RLSD) RECEIVE LINE SIGNAL DETECT 8
D6= (RI) RING INDICATOR 22
D5= (DSR) DATA SET READY 6
D4= (CTS) CLEAR TO SEND 5
(The bits below are 1 if state of bits above changed since
the last reading of this register.)
D3= (DRLSD) DELTA RECIEVE LINE SIGNAL DETECT 38
D2= (TERI) TRAILING EDGE RING INDICATOR 39
D1= (DDSR) DELTA DATA SET READY 37
D0= (DCTS) DELTA CLEAR TO SEND 36
------------------------------------------------------------------------
Summary of 8250A register locations for performing IO.
BASE+0 TX CHARACTER BUFFER if DLAB=0
BASE+0 LSB DIVSOR LATCH if DLAB=1
BASE+0 RX CHARACTER BUFFER if DLAB=0
BASE+1 MSB DIVSOR LATCH if DLAB=1
BASE+1 INTERRUPT ENABLE REG if DLAB=0 (IER)
BASE+2 INTERRUPT ID REGISTER (IIR)
BASE+3 LINE CONTROL REG (LCR)
BASE+4 MODEM CONTROL REG (MCR)
BASE+5 LINE STATUS REG (LSR)
BASE+6 MODEM SATUS REG (MSR)
------------------------------------------------------------------------
NOTE: Very little information was found on the 8259 interrupt controller
chip. What was found and could be verified to the best of my
knowledge is given below.
8259 Interrupt Controller Notes:
Acoording to research information,
Port Location 0x20 MUST BE SENT A 0x20 TO INDICATE AN EOI.
However in a review of BIOS async routines, no such EOI is sent.
It is used however to indicate a state change on the keyboard
interrupt BIOS routine.
Port Location 0x21 is the IRQ0-IRQ7 Hardware Interrupt Mask.
0=Interrupt Enabled, 1=Interrupt Disabled.
**************************************************************************/
#define SET_DLAB1 outportb(port[port_num]+3,(0x80|inport(port[port_num]+3)))
#define SET_DLAB0 outportb(port[port_num]+3,(0x7F&inport(port[port_num]+3)))
#define CLOCK_SPEED 1843200
/**** Set Baud Rate
void set_baud (short int port_num)
Sets the baud rate of an 8250 chip at the base address
on port_num.
Buad rate errors are minimal at baud rates <= 9600.
****/
void set_baud (short int port_num)
{
unsigned short int divisor;
divisor=CLOCK_SPEED/(baud[port_num]*16);
SET_DLAB1;
outport(port[port_num],divisor);
SET_DLAB0;
return;
} /* end set_baud() */
/**** Set frameing parameters on communications port.
void set_frame(short int port_num)
Sets the parity, bits/character, and number of stop bits.
port_num is used to get pointer to base address of 8250 chip.
Meaning of frame bits.
D7; DLAB
D6; 0=break disabled.
1=break enabled.
D5; 0=parity disabled.
1=parity enabled.
D4; 0=odd parity.
1=even parity.
D3; 0=no parity.
1=parity.
D2; 0=1 stop bit.
1=2 stop bits if bits/char > 5, else 1.5 stop bits.
D1-0;00=5 bits/char
01=6 bits/char
10=7 bits/char
11=8 bits/char
****/
void set_frame(short int port_num)
{
unsigned char f_byte,temp;
int i;
SET_DLAB0;
f_byte=0;
/* set parity */
if (parity[port_num] =='E' | parity[port_num]=='e') f_byte=0x3F;
if (parity[port_num] =='O' | parity[port_num]=='o') f_byte=0x2F;
/* set word length */
temp=wordlen[port_num]-5;
f_byte |=temp;
/* set stop bits */
if(!(2-stopbits[port_num])) f_byte |='\04';
/* configure port */
outportb(port[port_num]+3,f_byte);
return;
} /* end set_frame() */
